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Title:
MANUFACTURE OF SEMICONDUCTOR WAFER AND ANALYSIS THEREOF BY SIMS
Document Type and Number:
Japanese Patent JP2959352
Kind Code:
B2
Abstract:

PURPOSE: To accurately measure impurity on the surface of sample wafer by SIMS by solving problems accompanied in the manufacturing steps of a sample for analysis.
CONSTITUTION: A cap wafer 11 having an SOI structure is placed in close contact on the surface 2 of a semiconductor substrate (sample wafer) 1 to form a coupled wafer 21 through the heat treatment for two hours at 350°C under the N2 atmosphere. Thereafter, in regard to the cap wafer, the basic Si layer 12 is etched with a mixed solution of fluoric acid, nitric acid and pure water and the SiO layer 13 is then etched by fluoric acid to manufacture a semiconductor wafer 31 having the structure that a thin film Si layer 14 is provided on the surface 2 of the semiconductor substrate 1. This semiconductor wafer 31 is then subjected to analysis by SIMS. Since the semiconductor substrate is quickly capped, contamination of the semiconductor substrate surface can be prevented. Moreover, since coupling can be done with a low temperature heat treatment, impurity at the semiconductor substrate surface is never diffused into the inside and vaporization of substances which may be vaporized at a comparatively lower temperature during manufacture of sample can also be prevented.


Inventors:
SAITO HISASHI
ASAKO KIICHIRO
TSUDA NOBUHIRO
TAKENAKA TAKUO
Application Number:
JP1993000217985
Publication Date:
October 06, 1999
Filing Date:
August 10, 1993
Export Citation:
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Assignee:
SHINETSU HANDOTAI KK
International Classes:
G01N23/22; G01N23/225; H01L21/02; H01L21/306; H01L21/66; H01L27/12; (IPC1-7): H01L27/12; G01N23/22; H01L21/02; H01L21/306; H01L21/66
Domestic Patent References:
JP21914A
JP4132222A
Attorney, Agent or Firm:
Chieko Tateno