Title:
【発明の名称】数値演算処理装置
Document Type and Number:
Japanese Patent JP3096387
Kind Code:
B2
Abstract:
Arithmetic units are supplied with instructions from a control unit in common through an instruction broadcast bus. Each of the arithmetic units includes a process data input port, an address data input port, a process data output port and an address data output port. Address data appearing on the address ports specify addresses of a local memory. Each of the arithmetic units reads corresponding numeric data from the local memory and executes arithmetic processing in accordance with the instruction supplied from the control unit through a computing element group and a register group. In each arithmetic unit, it is possible to specify addresses of the local memory independently of each other. Each unit include circuitry for omitting an arithmetic operation on data read from the local memory when the read out data is negligible.
Inventors:
Yoshikazu Kondo
Yutaka Arima
Yutaka Arima
Application Number:
JP877794A
Publication Date:
October 10, 2000
Filing Date:
January 28, 1994
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
G06F15/18; G06F15/80; G06N3/02; G06N3/063; (IPC1-7): G06F15/18; G06F15/16
Domestic Patent References:
| JP4259085A | ||||
| JP4367084A | ||||
| JP561680A | ||||
| JP5242065A | ||||
| JP344758A | ||||
| JP2292689A | ||||
| JP2181257A | ||||
| JP5324694A | ||||
| JP443472A | ||||
| JP62166463A | ||||
| JP5346914A | ||||
| JP5189471A | ||||
| JP4280386A | ||||
| JP4237364A | ||||
| JP2294777A |
Attorney, Agent or Firm:
Fukami Hisaro (3 outside)