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Title:
MEMORY CONTROLLER
Document Type and Number:
Japanese Patent JPS5736488
Kind Code:
A
Abstract:

PURPOSE: To offer a memory controller in which RAMs can be used as sequential memories even if readout is not made with a given interval or it is faster than the write-in interval.

CONSTITUTION: The content of a write-in address pointer 1 is counted up sequentially one by one with a signal applied from a signal line (a) for write-in request to a memory section 4, it is applied to the memory section 4 via a multiplexer 3 as a write-in address, and DATA is written in this address sequentially. For readout request, first the write-in address data is set to a readout address pointer 2, and it is counted up by "1" to readout the oldest data stored in the memory section 4 and the data is read out from the memory section 4. Then, the address is counted up every readout.


Inventors:
IWATA KAZUHIRO
Application Number:
JP11090380A
Publication Date:
February 27, 1982
Filing Date:
August 12, 1980
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G06F3/08; G06F5/10; G11C7/00; (IPC1-7): G06F13/00; G11C7/00



 
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