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Title:
MEMORY DEVICE IN WHICH MEMORY CELLS HAVING MUTUALLY COMPLEMENTARY DATA ARE ARRANGED
Document Type and Number:
Japanese Patent JP2004103213
Kind Code:
A
Abstract:

To provide a memory device in which memory cells having mutually complementary data are arranged.

This memory device comprises a memory cell array block, first and second sense amplifiers, and first and second switches. In the memory cell array block, pairs of memory cell constituted of a memory cell and a complementary memory cell are arranged in a matrix state, the second pair of a memory cell and the complementary memory cell are arranged between the first pair of memory cell and connected to a first word line, the fourth pair of a memory cell and the complementary memory cell are arranged between the third pair of memory cell and connected to a second word line.


Inventors:
JEON BYUNG-GIL
CHOI MUN KYU
KIM KI-NAM
Application Number:
JP2003000286575
Publication Date:
April 02, 2004
Filing Date:
August 05, 2003
Export Citation:
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Assignee:
SAMSUNG ELECTRONICS CO LTD
International Classes:
G11C11/409; G11C5/06; G11C11/404; G11C11/405; (IPC1-7): G11C11/409; G11C11/405
Domestic Patent References:
JPH02231759A1990-09-13
JP2004103657A2004-04-02
JPH09147576A1997-06-06
Foreign References:
US6272054B12001-08-07
Attorney, Agent or Firm:
萩原 誠