To obtain a memory device which executes burst readout access and signal write access by inputting a single matrix address by combining the function of a field or a frame memory and the function of plural line memories.

A device is composed of a main memory array 2 and an auxiliary memory array 4 which is smaller in the number of rows than that of the main memory array 2 and these arrays share a same word line, an X decoder 6 and an internal data bus 24. A row address generator 12 generates a series of the row addresses based on a single staring row address which is designated by an external row address signal. A main row decoder MYD 8 decodes the row addresses to select a series of the rows inside the main memory array 2. An auxiliary row decoder SYD 10 decodes low-order bits of the row addresses to select a series of the rows inside the auxiliary memory array 4. By this way, the related plural pixel data are outputted from each frame with a signal combination burst.