PURPOSE: To omit a delay element by allowing a sense amplifier to make the conductance values of both MOS transistor (TR) pairs different in a precharged state.
CONSTITUTION: The memory device has a pair of PMOS TRs consisting of P-channel MOS TRs PM1, PM2 in which the gates and drains are mutually connected and respective sources are connected in common and a pair of NMOS TRs consisting of N-channel MOS TRs NM1, NM2 having similar relation. The sense amplifier deformed the threshold voltage Vth of the P-channel MOS TRs PM1, PM2 in the PMOS TR pair in order to make the conductance values of both the MOS TR pairs different from each other in the precharged state. Consequently, circuit constitution for delaying the operation of one MOS TR pair by a delay element, etc. can be omitted.
JPH04259994 | SEMICONDUCTOR MEMORY CIRCUIT |
WO/2020/145555 | TERNARY MEMORY CELL AND MEMORY DEVICE COMPRISING SAME |
JPH09106681 | TRANSISTOR CIRCUIT FOR CONFIRMING STATE OF BIT LINE |