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Patent Searching and Data


Title:
MEMORY MANAGEMENT SYSTEM
Document Type and Number:
Japanese Patent JPH04336627
Kind Code:
A
Abstract:

PURPOSE: To obtain a memory management system where the stack and local memory areas can be managed with high availability of the memories for a processor of a stack arithmetic system.

CONSTITUTION: A stack memory 40 includes the arithmetic stack areas 41 and the local variable areas 42 which are alternately arrayed. The base addresses of both areas 41 and 42 are shown by the 1st and 2nd stack base addresses 51 and 52 respectively. The size of the memory 40 used by a program under execution is calculated from an arithmetic stack pointer 61 and local variable number 62. When an interruption is produced, both addresses 51 and 52 are updated based on these addresses 51 and 52 and the calculated size of the memory 40. Then the base address of the memory 40 used by an interruption processing routine is decided.


Inventors:
NAGAI GORO
Application Number:
JP10916491A
Publication Date:
November 24, 1992
Filing Date:
May 14, 1991
Export Citation:
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Assignee:
FUJI ELECTRIC CO LTD
FUJI FACOM CORP
International Classes:
G06F9/34; G06F9/46; G06F9/48; (IPC1-7): G06F9/34; G06F9/46
Attorney, Agent or Firm:
Yoshiyuki Osuge