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Patent Searching and Data


Title:
METHOD AND APPARATUS FOR INTERFACING OF SERIAL DATA SIGNAL
Document Type and Number:
Japanese Patent JPH0653951
Kind Code:
A
Abstract:
PURPOSE: To provide a method and a device for interfacing a series data signal (TDATA) accompanied by a data clock signal (TCLK) to a circuit controlled by a comparatively high local clock signal. CONSTITUTION: The data clock signal is sampled by the local clock signal by using a D-type flip flop 4. The other D-type flip flop 7 stores a sample prior to that stored in the flip flop. It is judged which clock pulse LCLK1 or LCLK2 of the local clock passes through a gate so as to form the corrected clock signal LCLK 1 based on the two stored samples. The corrected clock signals are used for clocking third flip flops 10 and 11 reading the bit of a data signal. The corrected clock signals are used for clocking data through a shift register so that they can be converted into parallel formats.

Inventors:
PIITAA JIEI BUINSON
Application Number:
JP11200693A
Publication Date:
February 25, 1994
Filing Date:
May 14, 1993
Export Citation:
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Assignee:
TEXAS INSTRUMENTS INC
International Classes:
G06F5/06; H04L7/00; G06F13/38; H04L7/04; H04N7/035; (IPC1-7): H04L7/04; G06F13/38
Attorney, Agent or Firm:
Minoru Nakamura (6 outside)