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Patent Searching and Data


Title:
METHOD AND DEVICE OF OPERATING LINEAR FEEDBACK SHIFT REGISTER AS A SERIAL SHIFT REGISTER ACCOMPANIED BY CROSS-CHECKING LATTICE STRUCTURE
Document Type and Number:
Japanese Patent JPH03256297
Kind Code:
A
Abstract:

PURPOSE: To transfer data to an output terminal without change in data by loading a zero logical value into a bit register through a serial data input terminal and shifting them in series.

CONSTITUTION: A linear feedback registers 28, which is connected through sense lines 12, 14, 16, and 18, receives input data in series maintaining the parallel input lines at zero logical levels, and operates as a serial shift register. When FF bit register 21 is clocked by a clock 30, a register 21 propagates the contents in series to an output terminal 32 without changing the contents through the following register 21. When the load register 21 is loaded in series here, a multiplexer 24 is made possible. When a zero logical value is thus loaded through an input terminal 31 and the data are serially shifted through the register 21, they can be transferred to the output terminal 32 without changing the contents.


Inventors:
ROBAATO JIEI RITSUPU
Application Number:
JP26655890A
Publication Date:
November 14, 1991
Filing Date:
October 05, 1990
Export Citation:
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Assignee:
KUROSUCHIETSUKU TEKUNOROJII IN
International Classes:
G06F11/27; G11C19/00; G11C19/38; (IPC1-7): G11C19/00