Title:
METHOD AND EQUIPMENT FOR WIRING INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3277077
Kind Code:
B2
Abstract:
PURPOSE: To wire logic elements of an integrated circuit using metal lines of the optimum line width by changing the width of lines in the layout of the provisional wiring based on a transmission delay and then determining a wiring path of the lines whose width has been changed.
CONSTITUTION: A transmission delay is calculated using the width of lines in the layout of a provisional wiring and then the line widths are changed based on the calculation result. Out of the width-changed lines, those using a thicker metal wire than the standard one are serched for their wiring path in the order that the line width is thick. By this, the shorts that can be caused by the overlapping of the lines are lessened. For those using a thinner metal wire than the standard one, they are searched for their wiring path in the order that the line width is thin. By this, a larger wiring area can be left for the lines whose wiring path is determined later. Due to this method, a wiring process can be done easily.
Inventors:
Takaaki Aoki
Application Number:
JP21729794A
Publication Date:
April 22, 2002
Filing Date:
September 12, 1994
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/82; (IPC1-7): H01L21/82
Domestic Patent References:
| JP6223134A | ||||
| JP5102308A | ||||
| JP433169A | ||||
| JP6351656A | ||||
| JP5102306A |
Attorney, Agent or Firm:
Hidekazu Miyoshi (3 outside)