To obtain EEPROM's capable of collectively erasing a memory block to be erased.

A block selection circuit 60 is provided for memory blocks obtained by dividing a memory cell array having a NAND cell in a row direction and comprises storing means 29. The storing means 29 corresponding to the memory block to be erased stores a block selection flag of logic 1, and the storing means 29 corresponding to the memory block not to be erased stores a reset flag of logic 0. Erasing is performed by utilizing each of stored flags. By the block selection circuit 60 storing a block selection flag, a word line of the memory block to be erased is set to be at an erasing voltage, and by the block selection circuit 60 storing a reset flag, a word line of the memory block not to be erased is floating.