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Title:
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2002026122
Kind Code:
A
Abstract:

To realize accurate and highly reliable processing of interconnection trenches for eliminating short defects between trench interconnections by suppressing the expansion of an interconnection trench pattern caused, when forming the interconnection trench pattern in a lower hard mask by etching using an upper hard mask, in the formation of the interconnection trenches and connection holes, using the two layers of the hard masks.

A method of manufacturing a semiconductor device comprises formation of a connection hole 21 in a first insulation film 12 and formation of an interconnection trench 22 in a second insulation film 13, using a plurality of mask layers. These mask layers are formed by a method which includes a process of forming a first mask layer 14, formed of a material having the same quality as that of the first insulation film 12 on the second insulation film 13; a process of forming a second mask layer 15 on the first layer; a process of forming the interconnection trench pattern 16 in the second mask layer 15; a process of forming a third mask layer 31, formed of a material having the same quality as that of the first mask layer 14 on the interconnection trench pattern 16; and a process of forming a connection hole pattern 19 through the third mask layer 31 and the first mask layer 14.


Inventors:
MIYATA KOJI
Application Number:
JP2000201742A
Publication Date:
January 25, 2002
Filing Date:
July 04, 2000
Export Citation:
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Assignee:
SONY CORP
International Classes:
H01L21/3065; H01L21/768; H01L21/302; (IPC1-7): H01L21/768; H01L21/3065
Attorney, Agent or Firm:
Kuninori Funabashi