METHOD FOR MANUFACTURING SUBSTRATE IN WHICH CAVITY IS FORMED

Japanese Patent JP2007221110

A

To provide a method for manufacturing a substrate in which a cavity is formed.

The method for manufacturing the substrate in which a cavity is formed, comprises (a) a step of forming an upper layer circuit on an upper seed layer, (b) a step of laminating a dry film in a region, where a cavity is formed, of the upper seed layer, (c) a step of forming an insulating layer 330 on a top surface of the upper seed layer and a top surface and a side surface of the upper layer circuit to form an upper outer layer, (d) a step of laminating the upper outer layer on one surface of a core layer 310 on which an inner layer circuit 320 is formed, (e) a step of removing the upper seed layer, and (f) a step of removing the dry film to form the cavity. In the method for manufacturing the substrate in which the cavity is formed, by forming the insulating layer on the side surface of an outer layer circuit 340, total height of the substrate can be reduced while keeping the same height of the insulating layer.

COPYRIGHT: (C)2007,JPO&INPIT

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JP2009155668	PRETREATMENT LIQUID FOR PROMOTING STARTING OF ELECTROLESS PALLADIUM PLATING REACTION, ELECTROLESS PLATING METHOD USING THE PRETREATMENT LIQUID, CONNECTION TERMINAL FORMED BY THE ELECTROLESS PLATING METHOD, AND SEMICONDUCTOR PACKAGE USING THE CONNECTION TERMINAL AND ITS MANUFACTURING METHOD
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JUNG HOE KU
KANG MYUNG SAM
KIM JI-EUN
PARK JUNG-HYUN

JP2007007727A

August 30, 2007

January 17, 2007

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SAMSUNG ELECTRO MECH

H01L23/12; H01L25/065; H01L25/07; H01L25/18; H05K3/46

JPH0936549A	1997-02-07
JP2003243837A	2003-08-29
JPH01282892A	1989-11-14

Akihiro Ryuka

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