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Patent Searching and Data


Title:
METHOD AND MEMORY FOR PREDICTIVE READ OF SERIAL ACCESS MEMORY
Document Type and Number:
Japanese Patent JPH08235851
Kind Code:
A
Abstract:

To increase a maximum permissible internal access time and equalize an access time which is viewed from outside equal to that of standard constitution by making an address begin to be decoded according to the starting (q) bits of the address.

The starting (q) bits of the address ADD are stored in a subregister RI1 and the remaining (p) bits are stored in R12. When a word is read out, (q) bits of the word are decoded by a row decoding circuit LD and a column decoding circuit CD while the (q) and (p) address bits of the word are stored in the RI's, and binary information represented with the respective words in half arrays M1 and M2 is fetched to sense circuits SA1 and SA2. A control circuit CC decodes the (p) bits and the binary information of their word is derived to a terminal 3 by a multiplexer MUXS and an output register RO.


Inventors:
FURANSOWA TERIE
Application Number:
JP1995000317543
Publication Date:
September 13, 1996
Filing Date:
November 10, 1995
Export Citation:
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Assignee:
SGS THOMSON MICROELECTRONICS
International Classes:
G11C17/00; G11C7/10; G11C8/00; G11C8/04; G11C11/00; G11C16/02; (IPC1-7): G11C8/04; G11C16/06
Foreign References:
US5093805A1992-03-03
Attorney, Agent or Firm:
越場 隆