Title:
METHOD OF PRODUCING INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS6052047
Kind Code:
A
Abstract:
A method for manufacturing an integrated circuit device illustrates the preparation of the first surface of a circuit wafer including the placement of fine alignment indicia 34a outside the active chip area. A support wafer 50 is secured to the first surface of the circuit wafer 10 by an adhesive layer 58. The circuit wafer 10 is thinned. Openings 66 are photoshaped in the circuit wafer 10 using wafer flats 51 for alignment. The openings expose alignment indicia 34a which are relief images in the adhesive of the alignment pattern 34. The exposed surface of the circuit wafer 10 is photoshaped, using the indicia 34a for alignment, to define wafer segments 68 positioned over resistor doped regions 22.
Inventors:
REIMONDO AARU KURISUCHIYAN
JIYOSEFU SHII ZAACHIYAA
JIYOSEFU SHII ZAACHIYAA
Application Number:
JP13120784A
Publication Date:
March 23, 1985
Filing Date:
June 27, 1984
Export Citation:
Assignee:
TELETYPE CORP
International Classes:
H01L23/14; H01L21/02; H01L21/301; H01L21/304; H01L21/52; H01L21/58; H01L21/822; H01L23/544; H01L27/04; H01L27/12; (IPC1-7): H01L21/58; H01L21/78; H01L23/02; H01L23/12; H01L27/04
Domestic Patent References:
| JPS5717158A | 1982-01-28 | |||
| JPS5387163A | 1978-08-01 | |||
| JPS5893345A | 1983-06-03 | |||
| JPS5459083A | 1979-05-12 | |||
| JPS5283070A | 1977-07-11 | |||
| JPS5745254A | 1982-03-15 |
Attorney, Agent or Firm:
Masao Okabe