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Title:
METHOD FOR SIMULATING FAILURE OF COMBINATION CIRCUIT
Document Type and Number:
Japanese Patent JPH04147068
Kind Code:
A
Abstract:

PURPOSE: To speed up and save a memory in failure simulation processing by performing failure simulation and checking detectability of a failure in a circuit only when failure detection of a tip signal line is possible.

CONSTITUTION: A method for failure simulation of a combination circuit 4 primarily includes recognition of branch circuits 5a, 5b in a circuit 4. Then failure simulation by means of a simultaneous method is performed only with failures in tip signal lines 6a, 6b of the circuits 5a, 5b as targets. Only when detection of the failure in the signal lines 6a, 6b is possible, failure detectability in the circuits 5a, 5b is checked. Thus the number of failures to be treated is largely reduced so that calculation and storage can be largely reduced in volume in failure simulation.


Inventors:
NAKADA TSUNEO
Application Number:
JP27146090A
Publication Date:
May 20, 1992
Filing Date:
October 09, 1990
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F11/25; G06F11/26; G06F17/50; G01R31/28; (IPC1-7): G01R31/28; G06F11/26
Attorney, Agent or Firm:
Yu Sanada



 
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