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Title:
METHOD FOR SYNTHESIZING LOGIC FOR ENGINEERING CHANGE AND DEVICE THEREFOR
Document Type and Number:
Japanese Patent JP3234124
Kind Code:
B2
Abstract:

PURPOSE: To easily attain synthesis with a new logical network by converting each transistor gate into a logical gate having an output function which is the same as the output function, and changing one part of a logical network.
CONSTITUTION: A part to be corrected in a logical network is designated as a first part, and a part to be left as it is designated as a second part by a user according to engineering change. A third part can be freely changed. For example, when the user requests the elimination of connection 601 from a transistor gate 68 to a transistor gate 61, the gate 68 is included in the first part, and gates 61-64, inventors 71 and 72, and connection between them are included in the second part. On the other hand, the connection 601 included in the first part is the only fan out connection of the gate 68 so that the gate 68 and input connection 603 can be eliminated. Thus, a final transistor circuit can be obtained by combining a conventional logical network with a new logical network.


Inventors:
Muroga, Saburo
Application Number:
JP1995000071812
Publication Date:
December 04, 2001
Filing Date:
March 29, 1995
Export Citation:
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Assignee:
Muroga, Saburo
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Attorney, Agent or Firm:
伊東 忠彦 (外1名)