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Title:
METHOD FOR TESTING DELAY OF INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS649380
Kind Code:
A
Abstract:

PURPOSE: To easily judge with accuracy whether or not individual circuit sections appropriately operate in an actual integrated circuit by testing each chip by using a DC test pattern and judging whether or not the maximum allowable delay is exceeded at every signal route class.

CONSTITUTION: Firstly, a plurality of signal routes which are coupled between accessible terminals and at least one of which contains the latch of a scan register is set. Then the maximum allowable delay of each signal route which is decided by the design of an integrated circuit is decided and whether or not the actual delay exceeds the maximum allowable delay is judged on each signal route by measuring the actual delay on each signal route. Any circuit which exceeds the maximum allowable delay in any route is judged as unsatisfactory.


Inventors:
CHIYAO CHIYUN BE
CHIYAARUZU HAWAADO KAANERU
UIRIAMU RATSUSERU HERAA
ROBAATO BURUUSUTAA HITSUSUKOTS
FURANKO MOTEIKA
CHIYAARUZU EDOUIN RAATOKOU
PIIITAA JIYON SARUBUAATORII
ERUMAA MAASHIYARU SHIYAAPU
NANDAKUMAA NIICHIYANANDA TENRU
Application Number:
JP9582588A
Publication Date:
January 12, 1989
Filing Date:
April 20, 1988
Export Citation:
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Assignee:
IBM
International Classes:
G01R31/28; G01R31/3185; G01R31/317; (IPC1-7): G01R31/28
Domestic Patent References:
JPS5228613A1977-03-03
Attorney, Agent or Firm:
Kiyoshi Goda (4 outside)