Title:
MODE REGISTER SET CIRCUIT OF SEMICONDUCTOR DEVICE AND METHOD OF SETTING OPERATION MODE
Document Type and Number:
Japanese Patent JP3820559
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a mode register set circuit of a semiconductor device which requires preparing no additional control signal.
SOLUTION: An address signal level sensing part 201 receives an input signal Ai showing information on mode setting, and outputs a level sensing signal Ai' only when the voltage level of the input signal Ai is higher than the voltage level at the time of normal operation by a predetermined level. A power source voltage sensing part 203 outputs power source voltage sensing signal VCCHB activated when the power source voltage Vcc is not higher than a predetermined level. A logic gate 205 responds to the power source voltage sensing signal VCCHB and the level sensing signal Ai' and generates a mode signal PMODEi'. A latch part 207 latches the mode signal PMODEi' and outputs the reverse signal as a mode signal PMODEi.
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Inventors:
Hayashi Toru
Ginger Na Tin
Ginger Na Tin
Application Number:
JP26358698A
Publication Date:
September 13, 2006
Filing Date:
September 17, 1998
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G11C11/407; G11C11/413; G11C5/06; G11C7/12; G11C8/00; G11C11/401; G11C11/4074; G11C11/4094; H01L21/8234; H01L27/088; (IPC1-7): G11C11/407; G11C11/413; G11C11/401; H01L21/8234; H01L27/088
Domestic Patent References:
| JP3225692A | ||||
| JP64019589A | ||||
| JP57004616A |
Attorney, Agent or Firm:
Yasunori Otsuka
Kenichi Matsumoto
Kenichi Matsumoto
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