To secure higher failsafe performance, in a configuration of monitoring an operation of a controller such as a microcomputer using charging and discharging of a capacitor.
A charging/discharging control circuit 110 supplies a first current I1 through a first route, charges a capacitor 202, and discharges the capacitor 202 according to watchdog signals cyclically inputted from a controller 201. When a charging voltage of the capacitor 202 reaches a prescribed value, a signal output circuit 130 outputs signals indicating absence of the watchdog signals. When detecting supply stop of the first current I1 from the charging/discharging control circuit 110, a forced charging circuit 140 supplies a second current I2 larger than the first current I1 through a second route different from the first route, and charges the capacitor 202.
KIDO KEISUKE
KOMATSU KAZUHIRO
JPH05173841A | 1993-07-13 | |||
JPH07230395A | 1995-08-29 | |||
JPH1196044A | 1999-04-09 | |||
JPH05173841A | 1993-07-13 | |||
JPH07230395A | 1995-08-29 | |||
JPH1196044A | 1999-04-09 |