To prevent a reading failure caused by sneak current in a cross point memory array.
The cross point memory array is produced using a memory device 100. In the memory device 100, a resistance memory lower electrode 102, a resistance memory substance 104, a resistance memory upper electrode 106, an MSM lower electrode 108, a semiconductor layer 110, and an MSM upper electrode 112 are stacked in this order. In this configuration, the MSM lower electrode 108, the semiconductor layer 110, and the MSM upper electrode 112 form an MSM binary switch. The MSM binary switch has a high resistance under reverse bias. The cross current memory array is produced by using the memory device 100 in which the MSM binary switch and the resistance memory substance 104 are connected in series, thereby preventing current from passing in an undesired direction.
LI TINGKAI
JP2004281497A | 2004-10-07 |
WO2004084229A1 | 2004-09-30 | |||
WO2004084228A1 | 2004-09-30 |