Title:
マルチレベル・メモリ・ストレージ・システムにおけるマルチビット・エラー訂正の方法およびプログラム
Document Type and Number:
Japanese Patent JP4588806
Kind Code:
B2
Abstract:
A method, system, and computer software product for operating a collection of memory cells. Memory cells are organized into a group of memory cells, with each memory cell storing a binary multi-bit value delimited by characteristic parameter bands. Two adjacent characteristic parameter bands are assigned binary multi-bit values that differ by only one bit. In one embodiment, an error correction unit calculates an actual parity check value of the retrieved binary multi-bit values for the group of memory cells. If the actual parity check value is not equal to the expected parity check value, the error correction unit assigns the error memory cell a corrected binary multi-bit value with the characteristic parameter value within the characteristic parameter band adjacent to the characteristic parameter band associated with the retrieved binary multi-bit value such that calculating a second actual parity check value correctly indicates the parity for the group of memory cells.
Inventors:
Ram, Chang, Hong
Application Number:
JP2010513963A
Publication Date:
December 01, 2010
Filing Date:
July 01, 2008
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
G06F12/16; G11C29/42
Domestic Patent References:
JP2001332096A | ||||
JP2007157239A | ||||
JP11339496A |
Foreign References:
US20070086239 | ||||
EP0709776A1 |
Attorney, Agent or Firm:
Takeshi Ueno
Tasaichi Tanae
Yoshihiro City
Tasaichi Tanae
Yoshihiro City