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Title:
MULTILAYER CHIP BALUN DEVICE
Document Type and Number:
Japanese Patent JP2010199894
Kind Code:
A
Abstract:

To further reduce a device size with a coupled line being easily shortened to a length of λ/4 or shorter, and to eliminate deterioration of characteristics, as well as to carry out adjustment of a used frequency with ease and at low cost.

In a multilayer chip balun device, there are buried a set of a first coupled line 30 and a third coupled line 34 and a set of a second coupled line 20 and a fourth coupled line 16, each of which is electromagnetically coupled with the other and has a length of λ/4 or shorter (λ: used wavelength) in such a manner that the sets of lines are overlaid vertically with respect to a mounting surface inside a dielectric chip. One end of the first coupled line is connected to an unbalanced terminal and the other end of it is led to the second coupled line. The other end of the second coupled line is open, and both ends of the third and fourth coupled lines are connected between balanced terminals and ground terminals, respectively. The first coupled line is connected to the second coupled line via an inductor pattern 26.


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Inventors:
NISHIZAWA HIROBUMI
OKUBO NAOKI
Application Number:
JP2009041466A
Publication Date:
September 09, 2010
Filing Date:
February 24, 2009
Export Citation:
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Assignee:
FDK CORP
International Classes:
H01P5/10; H01F17/00; H01F19/06
Domestic Patent References:
JP2001144513A2001-05-25
Foreign References:
US20030001710A12003-01-02
Attorney, Agent or Firm:
Shigemi