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Patent Searching and Data


Title:
MULTIPLEX DATA PHASE CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JPH04360430
Kind Code:
A
Abstract:

PURPOSE: To prevent multiplex data bit deviation between LSIs with respect to the system interfacing the two kinds of LSI with a multiplex data.

CONSTITUTION: In the system having two kinds of LSIA,LSIB interfaced with a multiplex data, a 1st 1/n frequency divider clock generating section 4 of the LSIA controls a parallel/serial conversion section 1 to convert an n-bit parallel data into a serial data. A signal representing a channel 1 from the 1st 1/n frequency divider clock generating section 4 of the LSIA is received by a 2nd 1/n frequency divider clock generating section 5 of the LSIB to generate a 1/n frequency division clock and fed to a serial/parallel conversion section 2 of the LSIB, in which the data is converted into an n-bit parallel data with a phase of the 1/n frequency division clock. The converted parallel data is outputted to a clock takeover section 3 and a 3rd 1/n frequency division clock generating section 6 takes over a data by the system frame pulse.


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Inventors:
SUGAWARA AKIRA
IKUTA KOJI
Application Number:
JP1991000136042
Publication Date:
December 14, 1992
Filing Date:
June 07, 1991
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03M9/00; G06F1/12; H04J3/06; H04L7/00; (IPC1-7): H03M9/00; H04J3/06; H04L7/00