PURPOSE: To miniaturize hardware by finding out the multiplex processing logical OR operation of plural bit strings with a multiplex processing memory for writing a multiframe multiplexing bit string in each frame and an OR gate for finding out logical OR operation between the information of a current frame and that of the proceeding frame.

CONSTITUTION: A selector 1 switches a period for inputting a multiframe multiplexing bit string inputted from an input terminal 10 and a period for forming a holding circuit for the information of multiframe multiplex logical OR operation based upon the multiplex processing memory 2 and the logical OR gate 5 based on a control signal 12. On the other hand, a latest bit string of each N frame is passed through a gate 7, applied to a reset memory 3 through a logical OR circuit 8 and stored in the memory 3 as reset information under control based upon a control signal 12. Then, a memory 2 reset timing control gate 6 is opened by a control signal 13 and a gate insetted between the OR gate 8 and the memory 3 is opened to clear all the contents of the memory 3. Consequently, the increment of hard size can be suppressed.