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Patent Searching and Data


Title:
NON-VOLATILE SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH0668688
Kind Code:
A
Abstract:

PURPOSE: To keep dispersion of threshold value voltage of a memory transistor caused by emitting operation of electrons, for example, erasing operation within appropriate range and to make erasing time optimum.

CONSTITUTION: Erasing operation is performed by impressing the prescribed potential difference between control gate electrodes and source electrodes of memory transistors 1a-1d by a potential difference setting section 30. Also, verifying operation can be performed by detecting threshold value voltage of the memory transistors 1a-1d. In this case, the potential difference setting section 30 controls impressing time for potential difference or magnitude of potential difference based on a DETECT signal from a verifying circuit 8, that is, in accordance with threshold value voltage of the memory transistor. Thereby, over erasing can be efficiently prevented, while erasing time can be made optimum.


Inventors:
WATSUJI YUKIHIRO
MARUYAMA AKIRA
Application Number:
JP1993000160076
Publication Date:
March 11, 1994
Filing Date:
June 03, 1993
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
G11C17/00; G11C16/02; G11C16/16; G11C16/34; (IPC1-7): G11C16/06
Attorney, Agent or Firm:
井上 一 (外2名)