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Patent Searching and Data

Document Type and Number:
Japanese Patent JP3285412
Kind Code:

PURPOSE: To make it possible to write in based on F-N tunneling and minimize power consumption by making thinner the concentration of dopants in a second region than that of a first region around the lower part of a floating type electrode.
CONSTITUTION: In each cell of non-volatile memory 11 in a p type semiconductor substrate 2, there is installed an n+ type drain 3 which is a second region and an n+ type source 4 which is a first region, thereby forming a channel region 16 which is an electric path formable region on the surface of a board between the drain 3 and the source 4. A tunnel oxide film 18, which is a tunnel insulation film, is installed to the upper part of the channel region 16. A floating gate 12, which is a floating type electrode, is further installed high above in this area. The concentration of dopants in the drain 3 is made thinner than that of the source 4, thereby forming a depletion layer whose maximum width is thicker between the floating type electrode in the second region and the second region. It is, therefore, possible to prevent electrons from being scratched from the floating electrode to the second region during write in.

Shimoji, Noriyuki
Application Number:
Publication Date:
May 27, 2002
Filing Date:
May 21, 1993
Export Citation:
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International Classes:
G11B5/02; G11C16/02; G11C16/04; G11C16/06; G11C17/00; H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Attorney, Agent or Firm:
古谷 栄男 (外2名)