Title:
読出時間を短縮させる不揮発性半導体メモリ装置
Document Type and Number:
Japanese Patent JP4426082
Kind Code:
B2
Abstract:
A semiconductor memory device includes page buffers having load transistors, each of which supplies load current to bitlines. The device also has a load control circuit, which is commonly connected to gates of the load transistor, having two discharge paths. The load control circuit discharges the gate voltage via the first discharge path when a gate voltage applied to the gates in read operation is higher than a target voltage, and discharges the gate voltage via the second discharge path when the gate voltage arrives at the target voltage. Therefore, it is possible to quickly set the gate voltage to the target voltage.
Inventors:
Lee Suk-ken
Jin Xin Thousand
Jin Xin Thousand
Application Number:
JP2000334988A
Publication Date:
March 03, 2010
Filing Date:
November 01, 2000
Export Citation:
Assignee:
SAMSUNG ELECTRONICS CO.,LTD.
International Classes:
G11C16/06; G11C8/08; G11C16/02; G11C16/04; G11C16/08
Domestic Patent References:
| JP8321195A | ||||
| JP10228792A | ||||
| JP11015540A |
Attorney, Agent or Firm:
Makoto Hagiwara