Title:
NON-VOLATILE SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP2002334591
Kind Code:
A
Abstract:
To provide a non-voltage semiconductor memory in which the degree of freedom of layout can be improved.
Global bit lines GB are arranged on upper layers of respective switch groups Y2S00 to Y2S03 and Y2S10 to Y2S13 extending in the direction of row. That is, 32 lines of global bit lines GB connected respectively to 32 pieces of transistors Tr3 included in the switch group Y2S00 are provided on a upper layer of the switch group Y2S00, and 32 lines of global bit lines are provided on also upper layers of the other switch groups Y2S10 or the like. Each one line is connected to each global bit line GB from 128 main bit lines MB shared by memory cell arrays MCA00 and MCA02 and 128 main bit lines MB shared by memory cell arrays MCA01 and MCA03.
Inventors:
SUGAWARA HIROSHI
JINBO TOSHIKATSU
MIKI ATSUNORI
KUROKAWA NORIYUKI
USHIGOE KENICHI
JINBO TOSHIKATSU
MIKI ATSUNORI
KUROKAWA NORIYUKI
USHIGOE KENICHI
Application Number:
JP2001135774A
Publication Date:
November 22, 2002
Filing Date:
May 07, 2001
Export Citation:
Assignee:
NEC CORP
International Classes:
G11C16/06; G11C5/02; G11C7/18; (IPC1-7): G11C16/06
Domestic Patent References:
| JPH10209304A | 1998-08-07 | |||
| JP2000293994A | 2000-10-20 | |||
| JP2001052495A | 2001-02-23 | |||
| JPH0917979A | 1997-01-17 |
Attorney, Agent or Firm:
Masanori Fujimaki