Title:
ノーマリーオフＩＩＩ‐窒化物トランジスタ
Document Type and Number:
Japanese Patent JP6835736
Kind Code:
B2
Abstract:
A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.
Inventors:
Calid Farid
Navigne Tipirneni
Navigne Tipirneni
Application Number:
JP2017551696A
Publication Date:
February 24, 2021
Filing Date:
March 28, 2016
Export Citation:
Assignee:
Texas Instruments Japan Ltd.
Texas Instruments Incorporated
Texas Instruments Incorporated
International Classes:
H01L21/336; C23C16/34; C30B25/02; C30B29/38; H01L21/205; H01L21/28; H01L21/8236; H01L27/088; H01L29/41; H01L29/423; H01L29/78
Domestic Patent References:
| JP2013247363A | ||||
| JP2014527303A | ||||
| JP1094676A |
Foreign References:
| US20130313561 | ||||
| WO2009066434A1 | ||||
| US20100270559 | ||||
| US20110297961 |
Attorney, Agent or Firm:
Kyozo Katayose