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Title:
OFFSET CORRECTING CIRCUIT OF A/D CONVERTER
Document Type and Number:
Japanese Patent JPS6153829
Kind Code:
A
Abstract:

PURPOSE: To remove the difference in offset of each A/D converter accurately by converting an input analog signal and a reference voltage into a digital signal alternately through plural parallel A/D converters.

CONSTITUTION: When a switch SW20 is at a side (p), the input analog signal from a terminal 40 is inputted to A/D converters 10 and 11 and converted into 180° out-of-phase clocks 1 and 2 having the same period and their outputs are inputted to acquisition memories 14 and 15 in, for example, addressed 0∼1023. A switch control circuit 19 is operated with the output of an address counter 18 to place the SW20 at a side (g) and then the reference voltage ER50 is A/D- converted 10 and 11 and stored in addresses 1024∼2047 of the memories 14 and 15. When ER=0, data stored in the addresses 1024∼2047 of the memories 14 and 15 show offsets of the converters 10 and 11 and a CPU17 subtracts the data in the addresses 1024∼2047 from the data in the addresses 0∼1023 of the memories 14 and 15 and stores the results in a buffer memory 16, thus making offset corrections.


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Inventors:
TANAKA KATSUAKI
TAKEKOSHI MAMORU
Application Number:
JP1984000176388
Publication Date:
March 17, 1986
Filing Date:
August 23, 1984
Export Citation:
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Assignee:
IWATSU ELECTRIC CO LTD
International Classes:
H03M1/10; (IPC1-7): H03M1/10
Domestic Patent References:
JPS51128254A1976-11-09
JPS55130229A1980-10-08