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Title:
演算増幅回路
Document Type and Number:
Japanese Patent JP4434759
Kind Code:
B2
Abstract:
In an operational amplifier including first and second power supply terminals, first and second input terminals, and a first and second output terminals, a first differential amplifier circuit includes first and second MOS transistors with a common source connected to a first tail current source, first and second load resistors and a first non-doped MOS transistor connected between the first and second resistors and the second power supply terminal. A second differential amplifier circuit includes third and fourth MOS transistors with a common source connected to a second tail current source, third and fourth load resistors and a second non-doped MOS transistor connected between the third and fourth load resistors and the second power supply terminal. A first output circuit includes a fifth MOS transistor with a gate connected to the drain of the second MOS transistor, and a sixth MOS transistor with a gate and a drain connected to the drain of the fifth MOS transistor, and a second output circuit includes a seventh MOS transistor with a gate connected to the drain of the first MOS transistor, and an eighth MOS transistor with a gate and a drain connected to the drain of the seventh MOS transistor. A first intermediate circuit is connected between the drain of the third MOS transistor and the gate of the sixth MOS transistor, and a second intermediate circuit is connected between the drain of the fourth MOS transistor and the gate of the eighth MOS transistor.

Inventors:
Toshiyuki Eto
Application Number:
JP2004015648A
Publication Date:
March 17, 2010
Filing Date:
January 23, 2004
Export Citation:
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Assignee:
NEC Electronics Corporation
International Classes:
H03F3/45; H03F3/30; H03K3/286; H03K3/356; H03K4/02; H03K5/24
Domestic Patent References:
JP62216509A
JP63263824A
JP2002176322A
JP6085568A
JP11308057A
JP6268456A
Attorney, Agent or Firm:
Minoru Kudo