PURPOSE: To improve the processing performance by constituting so that a pipeline in an operating unit can be controlled, without breaking a principle of a successive control of an instruction.
CONSTITUTION: When executing an operating pipeline in a floating point operating unit (F unit), the executing cycle number is decided in advance, for instance, to 3. In case of processing an instruction which requires ≥3 cycles, for instance, the first instruction which requires 6 cycles, the operating pipeline can be executed during the last 2 cycles. Also, in case of an instruction of ≤3 cycles, for instance, a load system instruction, it is delayed to 3 cycles so that a principle of a successive control is observed. That is to say, when the load system instruction is executed, a data to be stored in a floating point register (FPR) 24 appears in a register 16. Also, when the load system instruction is executed, a data is set to a data register 33 through a code converting circuit 32 in an FEA cycle. A data which is converted in an FEB cycle is shifted to a data register 34. A data of the data register 34 is loaded on a signal line 102 through a multiplexer #35 in an FEC cycle.
WATANABE TAKESHI
WADA KENICHI
| JPS5466048A | 1979-05-28 | |||
| JPS52115640A | 1977-09-28 | |||
| JPS5710872A | 1982-01-20 | |||
| JPS5710875A | 1982-01-20 |