To remove an incorrect pulse when a reset pulse is inputted and when '0' level is continuously inputted and to accurately output a digital signal having a proper pulse width regarding burst input of an optical signal.
A peak detector 4 detects a peak value equivalent to '1' level of a voltage signal S2, and a zero level detector 5 detects a peak value equivalent to '0' level. A threshold arithmetic circuit 6 outputs an intermediate value of the peak values as threshold values to a limiter 3, and the limiter 3 determines a digital value depending upon whether a voltage signal S3 exceeds the intermediate value or not. A level detection circuit 7 compares a predetermined voltage Vth1 and the output of the signal S3 from the peak detector 4. When the signal S3 exceeds the predetermined voltage Vth1, a gate circuit 8 is 'opened' and a signal S6 determined by the limiter 3 is caused to pass and is outputted. When the signal S3 does not exceed the predetermined voltage Vth1, the gate circuit 8 is 'closed' and a signal S6 determined by the limiter 3 is cut off.
MOTOJIMA KUNIAKI
Next Patent: RADIO AZIMUTH INDICATOR