Title:
OSCILLATION CIRCUIT AND PLL CIRCUIT USING IT
Document Type and Number:
Japanese Patent JP3647147
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a voltage controlled oscillation circuit capable of generating a clock signal with a frequency not susceptible to dispersion in manufacture.
SOLUTION: An output N1 from an operational amplifier AMP 1 swings between constant voltages VRH and VRL depending on ON/OFF of switches S4, S5 and is compared with a constant voltage and a clock signal Vout (CLK) at an H or L level is generated. Then the increasing and decreasing speed (tilt) of the level of the node N1 depends on the level of an input voltage Vin and an output with a frequency according to the input voltage is generated.
Inventors:
Noboru Inaba
Yuji Segawa
Kunihiko Goto
Yuji Segawa
Kunihiko Goto
Application Number:
JP16927296A
Publication Date:
May 11, 2005
Filing Date:
June 28, 1996
Export Citation:
Assignee:
富士通株式会社
International Classes:
H04N5/12; H03H19/00; H03K3/0231; H03K4/02; H03L7/099; H03L7/183; (IPC1-7): H03K3/0231; H03L7/099
Domestic Patent References:
| JP6085625A | ||||
| JP60109332A | ||||
| JP50033754A | ||||
| JP64051710A | ||||
| JP59174015A | ||||
| JP60109332A | ||||
| JP50033754A |
Attorney, Agent or Firm:
Kenji Doi
Hayashi Tsunetoku
Hayashi Tsunetoku
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