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Title:
OUTPUT DECISION ERRONEOUS OPERATION DETECTOR CIRCUIT OF ELECTRONIC CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JPS54157073
Kind Code:
A
Abstract:

PURPOSE: To discriminate whether an output voltage is good or not and detect easily the erroneous operation of a noise margin test by only switching reference voltages for output decision test and noise margin test.

CONSTITUTION: At a function test time, terminal CD of a J-KFF is made of "L" by mode set circuit 5, and Q is made of "L" whichever values terminals J, K and CP have, and erroneous operation detector circuit 11 is not operated. Each part of output voltage decision circuit 9 performs a logical operation at this time; when the tested input is "H", LED2 of output voltage display circuit 13 is extinguished; and when the tested input is "L", LED2 is lit; and when the tested input is intermediate between "H" and "L", LED2 is flashed. At a noise margin test time, reference voltages 3 and 4 are switched by mode set circuit 5, and terminal CD is made of "H". Since FFJK1 has terminal JK connected to "H", output Q is inverted only at an input CP transition time of "H"→"L", and erroneous operations are easily detected even if the pulse width of square wave noise is narrow. Then, if a noise repeat frequency is selected, LED1 is flashed, and measurement becomes easy furthermore.


Inventors:
YUASA HIROYOSHI
Application Number:
JP6599478A
Publication Date:
December 11, 1979
Filing Date:
May 31, 1978
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC WORKS LTD
International Classes:
G06F11/24; H03K19/003; G01R31/30; (IPC1-7): G01R31/28; G06F11/00; H03K19/00
Domestic Patent References:
JPS50120745A1975-09-22
JPS5087255A1975-07-14



 
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