PURPOSE: To ensure the phase synchronism with a pulse of narrow width and also to secure the bit phase synchronism even for the normally received data even through the positive or negative pulse width of the received data varies and reduces.

CONSTITUTION: The received data D1 are delayed by a fixed phase amount by the delay means 41 to 55 of plural stages, and the data D1 and the data D2 to Dn are triggered by a clock signal CK and held by a flip-flop so. A changing point detection means 57 detects two changing points of different logics based on the held data Q1 to Qn on phases adjacent to each other, and a difference calculation means 76 calculates the phase difference between both changing points. A difference value decision means 77 outputs the phase difference that is smaller than one cycle of a signal CK. This phase difference is divided into 1/2 by a division means 78, and an addition means 79 adds the 1/2 phase difference value to the phase value of the first changing point. Then a selection means 80 selects the data D1 to Dn of the phases corresponding to the added phase value.