To attain the high speed of an access time by determining the transition from a selection condition by which a synchronous memory is made to a selection state and a non-selection condition to the selection state and enabling plural output pins.
When the inverse of a chip enable output disable signal 54 is in a high logical state, that is, the disable condition of a synchronous memory. This logical state shifts a node 2 to be in low state. The logical state is transferred to an output enable internal signal 112. The reason is that since a buffered clock signal 66 is in the high logical state and the output disable internal signal 114 is turned to be in the high logical state, an output pin is made to be in a tri-state state by the initial rising edge of the clock signal. Consequently, when the signal 66 is shifted to be in low state, a node 3 is transferred to the signal 112 and is held to be in the low logical state and an output disable internal signal 114 is held to be in a high state. This shows that a chip enable non-selection condition is to be quickly generated.
