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Patent Searching and Data


Title:
PLL CIRCUIT, AND CONTROL METHOD AND PROGRAM OF CONTROL VOLTAGE SUPPLIED TO VOLTAGE CONTROLLED OSCILLATOR IN PLL CIRCUIT
Document Type and Number:
Japanese Patent JP2008141583
Kind Code:
A
Abstract:

To solve a problem that in a digital terrestrial broadcasting system in which a SFN (single frequency network) is constructed for sending electric waves of an identical content at an identical time on an identical RF frequency from multiple transmitting stations, reception of transmission signals is disabled (SFN failure) in some areas where signals are redundantly received, when accuracy of a FFT clock of the transmission signals or transmission timings are misaligned.

When an error of an exterior synchronizing clock is detected, based on a control voltage traced and recorded in a time of normal operation, an inclination of change of the control voltage to the exterior synchronizing clock is estimated by calculation, and the calculated and estimated control voltage is determined as the control voltage supplied to a voltage controlled oscillator.


Inventors:
TAKADA TOMOHITO
Application Number:
JP2006327059A
Publication Date:
June 19, 2008
Filing Date:
December 04, 2006
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03L7/10; H03L7/087; H03L7/095; H04H20/18; H04H20/67; H04N5/04; H04H1/00; H04H3/00
Attorney, Agent or Firm:
Masahiko Desk
Naoki Shimosaka
Yasuhisa Tanizawa