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Patent Searching and Data


Title:
PLL CIRCUIT AND METHOD OF CONTROLLING THE SAME
Document Type and Number:
Japanese Patent JP2013026881
Kind Code:
A
Abstract:

To provide a PLL circuit and a method of control thereof which implement a wide range of changes in the oscillation frequency of a VCO while suppressing an increase in circuit scale.

A PLL circuit 1 includes a VCO 11, control logic 14 and a phase comparator 13. The VCO 11 has a variable capacitive element having a variable capacitance value depending on a potential difference between both ends, and outputs an output signal of an oscillation frequency depending on the potential difference. With a predetermined voltage applied to one end of the variable capacitive element, the control logic 14 determines a control voltage Vtc to be applied to the other end of the variable capacitive element on the basis of a frequency difference of an output signal from a reference signal. With a voltage at the other end of the variable capacitive element fixed at the control voltage Vtc determined by the control logic 14, the phase comparator 13 determines a control voltage Vta to be applied to the one end of the variable capacitive element on the basis of a phase difference of an output signal from the reference signal.


Inventors:
NAKAMURA YOSHIAKI
Application Number:
JP2011160681A
Publication Date:
February 04, 2013
Filing Date:
July 22, 2011
Export Citation:
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Assignee:
RENESAS ELECTRONICS CORP
International Classes:
H03L7/099; H03B5/08; H03K3/354; H03K4/50; H03L7/10
Attorney, Agent or Firm:
Ken Ieiri