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Title:
POLYPHASE DIGITAL FILTER
Document Type and Number:
Japanese Patent JPS5521676
Kind Code:
A
Abstract:

PURPOSE: To simplify the constitution of filter, by reducing the amount of multiplications required and making small the scale of hardware, through the use of the symmetry of the coefficient of the numerator of the transfer function.

CONSTITUTION: The multipliers 211 to 213 supplying the input from the input terminal 100 are provided, and the delay elements 231 to 232 of two frames are connected between the multipliers 211 to 213, and the output of the delay elements 231 and 232 and that of the multipliers 211 to 213 in the order from smaller to greater are added at the subtracter and adder 222 and 221. Further, the two frame delay elements 233 to 234 are connected between the multiliers 221 to 213, and the output of the multipliers 211 to 213 in the order of greater to smaller and that of the delay elements 223 and 224 are added at the addition and subtraction units 223 and 224. The output of the addition and subtraction unit 224 is fed to the adder 250 via the memory 240 and added and subtracted with the output of the addition and subtraction unit 221. Further, the output of the addition and subtraction unit 224 is delayed by one frame, the input data are converted in descending order and fed to the adder 250 to reduce the amount of multiplications required.


Inventors:
KANEMASA AKIRA
MARUTA RIKIO
Application Number:
JP9518378A
Publication Date:
February 15, 1980
Filing Date:
August 03, 1978
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H03H17/00; H03H17/02; H03H17/04; (IPC1-7): H03H17/02



 
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