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Patent Searching and Data


Title:
PREFETCH GENERATION PROGRAM AND COMPILER DEVICE
Document Type and Number:
Japanese Patent JP2010244208
Kind Code:
A
Abstract:

To prevent overwriting of necessary data on a cache memory, and to improve the efficiency of using a cache.

A compiler device 10 analyzes a source program, and decides whether the source program corresponds to a pattern of loop blocking dividing a memory area to be accessed into prescribed blocks. The compiler device 10 generates prefetch instructions to a block to be next processed when it is decided that the source program corresponds to the pattern of the loop blocking.


Inventors:
SUGIZAKI YOSHINORI
AOKI MASAKI
Application Number:
JP2009000090519
Publication Date:
October 28, 2010
Filing Date:
April 02, 2009
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F12/08
Domestic Patent References:
JP2000155689A2000-06-06
JP2000207224A2000-07-28
JPH11306167A1999-11-05
JPH05265770A1993-10-15
JP2002251321A2002-09-06
JP2005122506A2005-05-12
JPH10293692A1998-11-04
JPH10283192A1998-10-23
JPH10320212A1998-12-04
JPH10283192A1998-10-23
JPH10320212A1998-12-04
JP2000155689A2000-06-06
JP2000207224A2000-07-28
JPH11306167A1999-11-05
JPH05265770A1993-10-15
JP2002251321A2002-09-06
JP2005122506A2005-05-12
JPH10293692A1998-11-04
Foreign References:
WO2005078579A12005-08-25
WO2005078579A12005-08-25
Attorney, Agent or Firm:
酒井 宏明