PURPOSE: To elevate the reliability of a micro-instruction processing system, by executing the processing by use of the other block when an access error has occurred in one block, in a processing equipment for controlling a logical circuit by the micro-instruction.

CONSTITUTION: The memory capacity of a memory circuit 9 is divided into 2 blocks A, B, and a micro-instruction having the same contents is stored in the blocks A, B so as to be overlapped. When a parity error has occurred in a block A, it is stopped by an address which has generated the parity error. On the other hand, the micro-instruction is switched to the block B from the block A by a clock signal C and a parity error signal E. The micro-instruction which is read out from this block B is an address error. After that, contents of the block B are read out continously, and when a parity error occurrs, the operation is continued by switching to the block A.