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Title:
PROGRAMMABLE MEMORY BUILT-IN SELF-TEST COMBINING MICRO- CODE AND FINITE STATE MACHINE SELF-TEST
Document Type and Number:
Japanese Patent JP3640350
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To provide e programmable memory built-in self-test circuit combining a composite built-in type memory constitution composite micro-code and a finite state machine self-test.
SOLUTION: A finite state machine(FSM) is used for controlling generation of a signal applied to memory constitution in a self-test of hardware of the same chip as memory constitution. An area required for an instruction generator of a FSM base is smaller than the area required for storing its micro-code instruction, a built-in self-test(BIST) controller can provide modular architecture, and hardware design for BIST constitution can be used again. Consequently, a design cost for applying BIST constitution to new memory design is reduced. Successive characteristic when a finite state machine progress in a desired state is suitable especially for signal capture control in the case of access to a high speed data transfer circuit.


Inventors:
Earl Dean Adams
Thomas J. Eken Road
Stephen El Grego
Cam Ran Zalny
Application Number:
JP2001215624A
Publication Date:
April 20, 2005
Filing Date:
July 16, 2001
Export Citation:
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Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
G01R31/28; G01R31/3183; G01R31/3187; G06F11/22; G06F11/24; G06F12/16; G06F15/78; G11C29/02; G11C29/04; G11C29/12; G11C29/16; (IPC1-7): G11C29/00; G01R31/28; G01R31/3183; G06F11/22; G06F12/16; G06F15/78
Domestic Patent References:
JP10241399A
Attorney, Agent or Firm:
Hiroshi Sakaguchi
Yoshihiro City