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Title:
RAMP WAVE GENERATION CIRCUIT
Document Type and Number:
Japanese Patent JP2011035627
Kind Code:
A
Abstract:

To provide a ramp wave generation circuit capable of outputting ramp wave with fixed inclination, even when a capacitor with nonlinear C-V characteristics is used for an integration circuit.

For the integration circuit 2 to which MOS capacity C2 for integration with the nonlinear C-V characteristics is connected between input/output terminals of an operational amplifier OP2, in a current source portion 1, an operational amplifier OP1 compares charging voltage Vref of linear capacity Cref for reference with the fixed C-V characteristics to be charged by constant current I0 with charging voltage Vcal of MOS capacity Ccal for calibration having the same C-V characteristics as those of MOS capacity C2 for integration, and controls gate voltage of a PMOS transistor PT1 to control size of current I for charging the MOS capacity Ccal for calibration so that values of the charging voltage Vref and the charging voltage Vcal match with each other. A PMOS transistor PT2 to be controlled by the same gate voltage outputs the current I with the same size as that of current for charging the MOS capacity Ccal for calibration as charged current to the MOS capacity C2 for integration.


Inventors:
HITSU KAZUKI
Application Number:
JP2009179521A
Publication Date:
February 17, 2011
Filing Date:
July 31, 2009
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H03K4/501; H03M1/56
Attorney, Agent or Firm:
Hiroshi Horiguchi