To provide a receiving circuit which can measure bit error characteristics more accurately.

This circuit is provided with a pulse generating circuit 201 operating as a counter whose count value can be reset with an indication signal DET1 indicating that a previously received synchronous pattern is detected in a burst signal having part of a continuous pseudo-random pattern and this pulse generating circuit 201 outputs a count-up signal CO similar to the indication signal DET1 when counting up to the timing where the synchronous pattern of a burst signal having part of a continuous pseudo-random pattern which is received successively should be detected.