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Title:
RECEPTION SIGNAL DECIDING CIRCUIT
Document Type and Number:
Japanese Patent JPS5477523
Kind Code:
A
Abstract:

PURPOSE: To secure an accurate decision for the reception of the normal broadcast wave by detecting and integration the negative polar signals only in the horizontal synchronous signal period which is shorter than the horizontal blanking period and resetting the integrating circuit simultaneously with the end of the synchronous pulse signal.

CONSTITUTION: The output signal sent from the synchronous isolator circuit in the horizontal flyback period is supplied to terminal 1, and the horizontal blanking signal is supplied to termina l2. Thus, the negative polar signals are detected at the collector of transistor Tr7 only in the horizontal synchronous signal period which is shorter than the horizontal blanking period. For this detected signal, the pulse voltage is integrated via capacitor 12 and Tr8, and the integrating circuit is reset to the state before start of the integration in an extremely short time through the conduction of switch circuit 13 when the synchronous pulse signals supplied to the integrating circuit end. At the same time, the DC voltage corresponding to the output voltage amplitude of the integrating circuit is delivered (19). Thus, the reception of the normal broadcast wave can be decided accurately.


Inventors:
INOUE FUMIO
SUZUKI NOBUYUKI
Application Number:
JP1977000144846
Publication Date:
June 21, 1979
Filing Date:
December 02, 1977
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H04N5/14; H04N5/21; H04N5/44; H04N17/04; (IPC1-7): H04N5/14; H04N5/21