To provide a relaxation oscillation circuit that generates a more constant frequency clock than the prior art.
A clock generation sub-circuit 1 is controlled so as to alternately repeat a comparison voltage generation period of generating a comparison voltage Vcmp1 including a reference voltage Vref and an error voltage ΔV1 of a comparator 14 and outputting it as an output voltage Vsub1 to an inverting input terminal of the comparator 14, and a clock generation period of comparing an output voltage Vc1 from a current-voltage conversion circuit 11 with the comparison voltage Vcmp1. A clock generation sub-circuit 2 is also controlled so as to alternately repeat such a comparison voltage generation period and a clock generation period like the clock generation sub-circuit 1. A control circuit 5 controls the clock generation sub-circuits 1 and 2 such that one circuit is in the comparison voltage generation period while the other circuit is in the clock generation period.
HIROSE TETSUYA
OSAKI YUJI
| JP2001203563A | 2001-07-27 |
Mitsuo Tanaka
Kawabata Junichi
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