Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
RESIST TREATING METHOD
Document Type and Number:
Japanese Patent JPS62101027
Kind Code:
A
Abstract:

PURPOSE: To shorten time required for treating a resist while improving the heat resistance of the resist and the adhesive properties of a semiconductor wafer and the resist, to reduce the damage of a resist film and to treat the resist effectively by organically combining baking with the exposure of the emitted beams of a high- pressure mercury lamp containing strong ultraviolet rays.

CONSTITUTION: A semiconductor wafer 5 on which a pattern for a resist 4 is formed is placed on a wafer treating base 6. A shutter 3 is opened under the state in which the semiconductor wafer 5 is fast stuck to the wafer treating base 6 by vacuum- drawing a vacuum suction hole 7, and the resist 4 is irradiated by beams emitted from a high-pressure mercury lamp 1 without through the shutter 3. The wafer treating base 6 is heated at the same time as emitted-beam exposure or after a fixed time after emitted-beam exposure under the state in which vacuum suction is conducted. The wafer treating base 6 is heated for a proper time, and cooling water 11 is made to flow and the base 6 is cooled by water at the same time as heating is stopped or after a fixed time passes. The resist is cooled by water for a predetermined time, the shutter 3 is shut, emitted-beam exposure is brought into an extinction dimming state, and vacuum suction is released.


Inventors:
MIMURA YOSHIKI
Application Number:
JP1985000239455
Publication Date:
May 11, 1987
Filing Date:
October 28, 1985
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
USHIO ELECTRIC INC
International Classes:
G03F7/20; G03F7/38; H01L21/027; H01L21/30; H01L21/677; H01L21/683; (IPC1-7): G03F7/20; H01L21/30



 
Previous Patent: JPS62101026

Next Patent: DEVELOPING METHOD FOR WAFER