Title:
SDH INTERFACE TRANSMISSION CIRCUIT AND SDH INTERFACE RECEPTION CIRCUIT
Document Type and Number:
Japanese Patent JP3181205
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the circuit scale by providing an SOH, POS addition means, an H4 counter, and a VC assembly means to the circuit and relaying data received from a satellite channel to a ground channel network as SDH transmission data.
SOLUTION: A receiver side demodulates transmission data received from a satellite channel, a data extract section 11 detects a prescribed bit of a unique word in transmission data and an error correction code or the like and extracts succeeding reception data to the bit from a head because the data are burst data. On the other hand, an H4 counter 14 generates H4 bytes synchronously with the burst data and gives the data to a VC assembly section 5. The assembly section 5 inserts the H4 bytes to data extracted by the data extract section 11 in the order of multi-frames to assemble a virtual container of a VC-3. A POH is added to a container containing the data, and an SOH is added by an SOH addition section 7, and the result is relayed to a ground network as an STM-1 signal. The data are sent as burst data in the satellite channel.
Inventors:
Terutaka Taniguchi
Kazuyasu Okada
Yutaka Yamaguchi
Atsushi Ohta
Kazuyasu Okada
Yutaka Yamaguchi
Atsushi Ohta
Application Number:
JP21877695A
Publication Date:
July 03, 2001
Filing Date:
August 28, 1995
Export Citation:
Assignee:
Mitsubishi Electric Corporation
Nippon Telegraph and Telephone Corporation
Nippon Telegraph and Telephone Corporation
International Classes:
H04J3/00; H04B7/212; H04L7/00; (IPC1-7): H04J3/00
Domestic Patent References:
| JP4278744A | ||||
| JP522271A |
Other References:
電子情報通信学会秋季大会講演論文集，ＳＢ−３−６（１９９４−９−５），ＥＴＳ−ＶＩ実験用１５６Ｍｂ／ｓＳＳ−ＴＤＭＡシステムの構成と性能
Attorney, Agent or Firm:
Kaneo Miyata (1 person outside)